1. Field
The present invention relates to methods for computing and controlling power modes for a System on Chip (SoC). More particularly, the present invention relates to global power management of an SoC.
2. Description of Related Art
Global power management is becoming an increasingly important issue as energy costs continue to increase. In addition, by reducing power consumption and extending battery life in applications that may include mobile applications and portable media players, power control management provides the ability to increase functionality without having to increase power capacity and size of the devices. Global power management semiconductor is a market that is expected to undergo significant growth in the near-future.
There have been recent attempts at controlling power modes of semiconductors. For example, in the Open Multimedia Application Platform (OMAP), a Texas Instruments microprocessor, and more particularly, OMAP3, one of the mechanisms used that is available in Linux, called “CPUidle” The “CPUidle” is initialized with a table of possible global power modes, and includes properties on which the CPUidle can decide when to switch from one power mode to another power mode. The CPUidle framework includes a governor, which decides the target state C of the system; a CPUidle driver populates the C states supported by the system and implements functions to transition to the C states; and generic CPUidle framework, wherein every time the idle loop is called, this framework calls the current governor to decide the target state C of the system. This framework also calls the current driver to transition to the C state selected by the governor.
In addition, it is known that every driver implements suspend/resume after registration with the Linux Driver Model (LDM). The drivers release clocks and then save the context in a suspend call and restore these when “resume” is called. Also, drivers which have already released their clocks and have saved their context need not do anything in their suspend call.
However, one problem with a global (top-down) power management controller is that the controller has to query a lot of data regarding the current state of the SoC in order to decide which power mode is most appropriate. For example, when querying such information, virtually all details regarding the SoC are needed (e.g. an address map of all peripherals, etc.).
If both clocks and Vdd are managed, simple reference counting cannot be applied. For example, when the reference count of a Vdd reaches zero after a last decrement, the Vdd cannot necessarily be disabled. As Vdd=0, this means that all state (registers) of a hardware block will be lost. Hence, before disabling a Vdd, a state saving is required. Such a saving takes time, and the decision as whether or not to disable a Vdd-when the reference count reaches 0, must take into account how long the expected idle time (is w.r.t. the time that saving takes).
In general, disabling a clock is typically a good idea as it takes only a few cycles. However, disabling a Vdd needs a more elaborate trade-off, and the cost in cycles it takes to make the transition. Moreover, if the SoC has embedded Vdd switches, the trade-off is even more complicated. For example, There is a case where two hardware blocks (A and B) both have the same Vdd supply, but A also has a Vdd switch. As a result, A can be powered down by opening the switch or by Vdd going to zero (or both).